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CXP508L4/508L6
CMOS 4-bit Single Chip Microcomputer For the availability of this product, please contact the sales office.
Description The CXP508L4/508L6 is a CMOS 4-bit microcomputer which consists of 4-bit CPU, ROM, RAM, I/O port, 8-bit timer, 8-bit timer/counter, 18-bit time base timer, 8-bit serial I/O, vector interruption, and a liquid crystal displayer (LCD) controller/driver. They are integrated into a single clip with the standby function etc. which are to be operated at low power consumption. Features * Instruction cycle * ROM capacity * 64 pin SDIP (Plastic) 64 pin QFP (Plastic)
* *
* * * *
* * * *
4s/2MHz (2.4V to 3.5V) 4.096 x 8 bits (CXP508L4) 6.144 x 8 bits (CXP508L6) RAM capacity 400 x 4 bits (24 x 4 bits is used in combination with the LCD display memory) 32 general purpose I/O ports (For 16 segment outputs) LCD controller/driver (Direct drive possible) -- Optical specification of 24, 20 or 16 segment outputs -- 1/2, 1/3, 1/4 duty selectable through program -- 1/3 bias 2 external interruption input pins 8-bit/4-bit variable serial I/O 8-bit timer, 8bit timer/event counter and 18-bit time base timer are independently controllable Arithmetic and logical operations possible between the entire RAM area, I/O area and the accumulator by means of memory mapped I/O Reference to the entire ROM area is possible with the table look-up instruction 2 types of power down models, sleep and stop 64-pin plastic SDIP/QFP available Piggy back package (CXP5080) available
Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E95108-ST
CXP508L4/508L6
Block Diagram
(Enables to specify the I/O with bit unit)
(Enables to specify the I/O with port unit) 4 4 Port D
(Combines use of mask with segment output, optional) 4 Port E 4 Port F
Port A
Port B
Port C
Register
ALU Accumulator
Program counter (13)
Data memory 400 x 4 bits Stack
Flag Program memory Timer (8) Timer/Counter (8) 6144 x 8 bits (CXP508L6) 4096 x 8 bits (CXP508L4)
Data memory
Serial I/O (8) Interrupt control
Instruction control
LCD controller/driver VL VLC1 VLC2 VLC3 8 16 4
Time base timer (18)
Port X
Port Y
Clock control
EXTAL XTAL
PX3/SI PX2/SOA PX1/SOB PX0/SC
PY3/EC PY2/INT2 PY1 PY0
SEG16 SEG0 COM0 to to to SEG23 SEG15 COM3 (Common with Port E, Port F)
(Common with serial I/O)
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WP INT1 VDD VSS RST
CXP508L4/508L6
Pin Configuration (Top View)
VL XTAL EXTAL RST WP INT1 PY0 PY1 INT2/PY2 EC/PY3 SC/PX0 SOB/PX1 SOA/PX2 SI/PX3 PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PA0 PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD VLC3 VLC2 VLC1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1 SEG18/PF2 SEG19/PF3 SEG20/PE0 SEG21/PE1 SEG22/PE2 SEG23/PE3
EXTAL
COM0
COM1
COM2
INT1
XTAL
RST
WP
VDD
VLC3
VL
VLC2
VLC1
PA3 NC Vss
64 63 62 61 60 59 58 57 56 55 54 53 52 PY0 PY1 INT2/PY2 EC/PY3 SC/PX0 SOB/PX1 SOA/PX2 SI/PX3 PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1
20 21 22 23 24 25 26 27 28 29 30 31 32
PE3/SEG23
PE2/SEG22
PE1/SEG21
PE0/SEG20
PF3/SEG19
PF2/SEG18
PB3
PA0
PA1
PA2
PA3
Vss
NC
Note) Do not make any connection to NC pin.
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CXP508L4/508L6
Absolute Maximum Ratings Item Power supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD VLC1, VLC2, VLC3 VIN VOUT IOH IOH IOL IOL Topr Tstg PD Symbol Ratings -0.3 to +5.0 -0.3 to +5.01 -0.3 to +5.01 -0.3 to +5.01 -5 -50 15 50 -20 to +75 -55 to +150 1000 600 Unit V V V V mA mA mA mA C C mW mW
(Ta = -20 to +75C, VSS = 0V) Remarks
General purpose port2: per pin Entire pin total General purpose port2: per pin Entire pin total
SDIP QFP
1 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V. 2 The PE and PF are specified when PA to PD, PX0 to PX2, PY0, PY1 and mask option are port selected. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Power supply voltage Symbol VDD VLC1, VLC2, VLC3 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr Min. 2.4 2.0 Max. 3.5 3.5 Unit V V Remarks Guaranteed range during operation Guaranteed data hold operation range during STOP Liquid crystal power supply voltage1 (VSS = 0V)
LCD bias voltage
VSS 0.7VDD 0.8VDD VDD - 0.4 0 0 -0.3 -20
VDD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75
V V V V V V V C
Hysteresis input2 EXTAL pin3 Hysteresis input2 EXTAL pin3
1 The optimum value is determined by the characteristics of the liquid crystal display element used. 2 They are the respective pins of INT1, WP, PX0, PX3, PY2, PY3 and RST. 3 Specified only during external clock input.
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CXP508L4/508L6
Electrical Characteristics DC characteristics Item Symbol Pin Condition VDD = 2.4V, IOH = -0.3mA2 High level output voltage VOH PA to PF1, PX0 to PX2, PY0, PY1, VL (VOL only) VDD = 2.4V, IOH = -0.5mA2 VDD = 2.4V, IOH = -5A3 VDD = 2.4V, IOH = -10A3 VDD = 2.4V, IOL = 1.0mA VDD = 2.4V, IOL = 2.0mA EXTAL4 RST5 PA to PF6, PX0 to PX26, PX38, PY07, PY17, PY28, PY38, INT18, WP8, RST5 COM0 to COM3 VDD = 3.5V, VIH = 3.5V
(Ta = -20 to +75C, VSS = 0V) Min. 1.8 1.4 1.8 1.4 0.4 0.6 0.3 -0.3 VDD = 3.5V, VIL = 0.4V -1.5 20 -20 -200 -1.0 VDD = 3.5V VI = 0, 3.5V Typ. Max. Unit V V V V V V A A A mA
Low level output voltage
VOL IIH
Input current
IILE IILR IIL
High impedance IIZ I/O leakage current Common output impedance Segment output impedance
5
A
RCOM RSEG
VDD = 3.5V VLC1 = 2.65V VLC2 = 1.75V SEG0 to SEG15 1 VLC3 = 0.88V SEG16 to SEG23 VDD = 3.5V During external clock 1MHz operation Entire output pins open SLEEP mode STOP mode VLC1 to VLC3, COM0 to COM3, Clock 1MHz SEG0 to SEG15, 0V other than the measured SEG16 to SEG231, pins Other pins than VDD, VSS
3 5
5 15
k k
IDD Current power supply VDD IDDSP IDDS
1.3 0.6
4 1.2 7
mA mA A
Input capacitance
CIN
10
20
pF
1 The PE to PF show when the combined pins are selected as the port, and SEG16 to SEG23 show when the combined pins are selected as the segment output. 2 It is when the respective pins of PA to PF and PX0 to PX2 select the 3-state output circuit, and PY0 and PY1 are when the inverter output circuit is selected. 3 It is when the respective pins of PA to PF, PX0 to PX2, PY0 and PY1 select the pull-up resistance. 4 It is when the crystal or ceramic oscillation circuit is selected. 5 The RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. 6 The respective pins of PA to PF and PX0 to PX2 specify the input current when the pull-up resistance is selected, and specify the leakage current when in the port state during the 3-state output circuit or standby is selected at high impedance. 7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistance is selected, and specify the leakage current when in the port state during standby is selected at high impedance. 8 The respective pins of PX3, PY2, PY3, INT1 and WP only specify the leakage current. -5-
CXP508L4/508L6
AC characteristics (1) Clock timing Item System clock frequency System clock input pulse width Symbol fc Pin XTAL EXTAL EXTAL EXTAL EC EC
(Ta = -20 to +75C, VDD = 2.4 to 3.5V, VSS = 0V) Condition Fig. 1., Fig. 2. Fig. 1., Fig. 2.1 External clock drive Fig. 1., Fig. 2.1 External clock drive Fig. 3. Fig. 3. Min. 0.5 230 200 Max. Unit 2 MHz ns ns s 20 ms
tXL tXH System clock input rising and falling tCR times tCF tEL Event count clock input pulse width tEH Event count clock input rising and tER falling times tEF
tsys2 + 0.05
1 The external clock in Fig. 2. specified only when the option is selected for crystal or ceramic oscillation. 2 tsys = 8/fc Note) When adjusting the frequency accurately, there may be cases in which they may differ from Fig. 2. Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applying condition
Crystal oscillation Ceramic oscillation External clock1
EXTAL
XTAL
EXTAL
XTAL
C1
C2
OPEN
Fig. 3. Event count clock timing
0.8VDD EC 0.2VDD
tEH
tEF
tEL
tER
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CXP508L4/508L6
(2) Serial transfer Item Serial transfer clock (SC) cycle time Serial transfer clock (SC) high and low level widths Serial data input setup time (against SC ) Serial data input hold time (against SC ) High data3 output delay time from the SC falling time Symbol Pin SC
(Ta = -20 to +75C, VDD = 2.4 to 3.5V, VSS = 0V) Condition Input mode Output mode input mode Output mode1 Output mode2 SI SC input mode SC output mode SC input mode SC output mode Min. Max. Unit s s s s s s s s s
tKCY tKH tKL tSIK tKSI
SC
tsys/4 + 1.42 tsys tsys/8 + 0.7 tsys/2 - 0.1 tsys/2 - 1.6
0.1 0.2
tsys/8 + 0.5
0.1
SI SOA SOB SOA SOB SOA SOB
tKSOA tKSOB High data4 output delay time tKSOA from the SC falling time tKSOB tKSOA Low data output delay time from the SC falling time tKSOB
tsys/8 + 0.5 tsys/8 + 1.6 tsys/8 + 0.5
s
s
s
Note 1) tsys = 8/fc Note 2) The load of data output delay time is 50pF + 1TTL. 1 It is specified when SC pin is selected to the 3-atate output by the mask option. 2 It is specified when SC pin is selected to the pull-up resistance by the mask option. As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock frequency fc. 3 It is specified when SOA and PX1/SOB pins are selected to the 3-state output by the mask option. 4 It is specified when SOA and PX1/SOB pins are selected to the pull-up resistance by the mask option.
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CXP508L4/508L6
Fig. 4. Serial transfer timing
tKCY tKL tKH
SC
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD SI Input data 0.2VDD
tKSOA tKSOB
0.8VDD SOA SOB 0.2VDD Output data
(3) Others Item External interruption high and low level widths Reset input low level width Wake-up input high level width Note) tsys = 8/fc Symbol Pin INT1 INT2 RST WP
(Ta = -20 to +75C, VDD = 2.4 to 3.5V, VSS = 0V) Condition During edge detection mode Min. Max. Unit s s s ns s
tI1H, tI1L tI2H, tI2L tRSL tWPH
tsys + 0.05 tsys + 0.05
2tsys 500
STOP mode SLEEP mode
tsys + 0.05
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CXP508L4/508L6
Fig. 5. Interruption input timing
tI1L tI1H
INT1 (Rising edge)
0.8VDD 0.2VDD
tI1H
tI1L
INT1 (Falling edge)
0.8VDD 0.2VDD
tI2L
tI2H
0.8VDD INT2 0.2VDD
Fig. 6. Reset input timing
tRSL
RST 0.2VDD
Fig. 7. Wake-up input timing
tWPH 0.8VDD WP
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CXP508L4/508L6
Notes on Operation See Fig. 8., Additive capacity calculation chart, when using the crystal oscillator and select the appropriate capacity. Fig. 8. Crystal oscillation circuit additive capacity calculation chart (Ta = -20 to +75C, VDD = 2.4 to 3.5V)
200
C-Additive capacity [pF]
EXTAL 150 C1 100
XTAL
C2 C1 = C2 = C
50
0.1
1
5 f-Crystal oscillation frequency [MHz]
100
Note) The above chart shows a range in which the average quartz resonator has a relatively fast oscillation rising edge and stable characteristics. The capacity should be selected to correspond to the appropriate constant for each quartz resonator, should the frequency of the quartz resonator be accurately adjusted. Fig. 9. Shows recommended circuit and oscillators. Use the trimmer capacitor to C1, in the case of accurate adjustment of the oscillation frequency. Fig. 9. Recommended oscillation circuit Manufacturer
EXTAL XTAL Rd C1 C2
Model CSA2.00MG040
Frequency 2.00MHz 2.00MHz
C1 100pF -- (built in)
C2 100pF -- (built in)
Rd -- --
MURATA MFG CO., LTD.
CST2.00MG040
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CXP508L4/508L6
Package Outline
Unit: mm
64PIN SDIP (PLASTIC) 750mil
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15 32 0.5 0.1 0.9 0.15
1 1.778
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 8.6g
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
3 MIN
0.5 MIN + 0.4 4.75 - 0.1
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
19 + 0.35 2.75 - 0.15 0.12 M 0.8 0.2 EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER /42 ALLOY 1.5g
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
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16.3

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